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LAN91C110 REV. B
PRELIMINARY
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
FEATURES
Dual Speed CSMA/CD Engine (10 Mbps and 100 Mbps) Compliant with IEEE 802.3 100BASE-T Specification Supports 100BASE-TX, 100BASE-T4 16 Bit Wide Data Path (into Packet Buffer Memory) Generic 16-bit System Level Interface Easily Adaptable to ISA, PCMCIA (16-bit CardBus), and Various CPU System Interfaces Support for 16 and 8 Bit CPU Accesses Asynchronous Bus Interface 128 Kbyte External Memory Built-in Transparent Arbitration for Slave Sequential Access Architecture Early TX, Early RX Functions Flat MMU Architecture with Symmetric Transmit and Receive Structures and Queues IEEE-802.3 MII (Media Independent Interface) Compliant MAC-PHY Interface Running at Nibble Rate MII Management Serial Interface IEEE-802.3u Full Duplex Capability 144 Pin TQFP Package (1.0 Millimeter Height)
GENERAL DESCRIPTION
The LAN91C110 is designed to facilitate the implementation of second generation Fast Ethernet PC Card adapters and other non-PCI connectivity products. The LAN91C110 is a digital device that implements the Media Access Control (MAC) portion of the CSMA/CD protocol at 10 and 100 Mbps, and couples it with a lean and fast data and control path system architecture to ensure that the CPU to packet RAM data movement does not cause a bottleneck at 100 Mbps. The LAN91C110 implements a generic 16-bit host interface which is adaptable to a wide range of system buses and CPUs. This makes the LAN91C110 ideal for 10/100 Fast Ethernet implementations in systems based on system buses other than PCI. Total memory size is 128 Kbytes, equivalent to a total chip storage (transmit plus receive) of 64 outstanding packets. The LAN91C110 is software compatible with the LAN9000 family of products in the default mode and can use existing LAN9000 drivers (ODI, IPX, and NDIS) with minor modifications in 16 and 32 bit Intel X86 based environments. Memory management is handled using a unique patented MMU (Memory Management Unit) architecture and an internal 32-bit wide data path. This I/O mapped architecture can sustain back-to-back frame transmission and reception for superior data throughput and optimal performance. It also dynamically allocates buffer memory in an efficient buffer utilization scheme, reducing software tasks and relieving the host CPU from performing these housekeeping functions. The total memory size is 128 Kbytes (external), equivalent to a total chip storage (transmit and receive) of 64 outstanding packets. FEAST provides a flexible slave interface for easy connectivity with industry-standard buses. The host interface is "ISA-like" and is easily adapted to a wide range of system and CPU buses such as ISA, PCMCIA, etc. An IEEE-802.3 compliant Media Independent Interface (MII) provided on the network side of the LAN91C110. The MII interface allows the use of a wide range of MII compliant Physical Layer (PHY) devices to be used with the LAN91C110. The LAN91C110 also provides an interface to the two-line MII serial management protocol.
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ORDERING INFORMATION
Order Number: LAN91C110TQFP
80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123
Copyright (c) SMSC 2004. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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TABLE OF CONTENTS FEATURES................................................................................................................................1 GENERAL DESCRIPTION ........................................................................................................1 FUNCTIONAL DESCRIPTION ..................................................................................................9 DATA STRUCTURES AND REGISTERS...............................................................................13 TYPICAL FLOW OF EVENTS FOR TRANSMIT (AUTO RELEASE = 0) ..................................................36 TYPICAL FLOW OF EVENTS FOR TRANSMIT (AUTO RELEASE = 1) ..................................................37 TYPICAL FLOW OF EVENTS FOR RECEIVE.....................................................................................38 OPERATIONAL DESCRIPTION .............................................................................................46 MAXIMUM GUARANTEED RATINGS* ...................................................................................46 DC ELECTRICAL CHARACTERISTICS..................................................................................46 TIMING DIAGRAMS ................................................................................................................49 LAN91C110 REV. B REVISIONS ..........................................................................................55
LIST OF TABLES TABLE 1 - DESCRIPTION OF PIN FUNCTIONS........................................................................................................5 TABLE 2 - BUFFER TYPES ..........................................................................................................................................7 TABLE 3 - INTERNAL I/O SPACE MAPPING.....................................................................................................................16 TABLE 4 - PIN PACKAGE OUTLINE TABLE ....................................................................................................................54 LIST OF FIGURES FIGURE 1 - PIN CONFIGURATION .............................................................................................................................4 FIGURE 2 - LAN91C110 BLOCK DIAGRAM ..............................................................................................................8 FIGURE 3 - LAN91C110 SYSTEM DIAGRAM............................................................................................................8 FIGURE 4 - LAN91C110 INTERNAL BLOCK DIAGRAM WITH DATAPATH......................................................12 FIGURE 5 - DATA PACKET FORMAT ......................................................................................................................13 FIGURE 6 - INTERRUPT STRUCTURE .....................................................................................................................31 FIGURE 7 - INTERRUPT SERVICE ROUTINE .........................................................................................................39 FIGURE 8- RX INTR ....................................................................................................................................................40 FIGURE 9 - TX INTR....................................................................................................................................................41 FIGURE 10 - TXEMPTY INTR (ASSUMES AUTO RELEASE OPTION SELECTED) ............................................................42 FIGURE 11 - DRIVE SEND AND ALLOCATE ROUTINES......................................................................................43 FIGURE 12 - INTERRUPT GENERATION FOR TRANSMIT, RECEIVE, MMU ....................................................45 FIGURE 13 - ASYNCHRONOUS CYCLE - NADS=0.................................................................................................49 FIGURE 14 - ASYNCHRONOUS CYCLE - USING NADS ........................................................................................49 FIGURE 15 - ADDRESS LATCHING FOR ALL MODES..........................................................................................50 FIGURE 16 - SRAM INTERFACE ...............................................................................................................................51 FIGURE 17 - MII INTERFACE ........................................................................................................................................53 FIGURE 18 - 144 PIN TQFP PACKAGE OUTLINES.........................................................................................................54
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A10 A11 VDD A12 A13 A14 A15 GND nBE0 nBE1 D7 nLDEV D6 D5 D4 GND D3 D2 D1 D0 ARDY GND INT0 nRD VDD nWR RESET GND MCLK AEN AUISEL MDO MDI AGND N/C AVDD 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
nLNK XTAL1 XTAL2 VDD nCSOUT TX25 RX_ER RX_DV GND RX25 COL100 CRS100 RXD0 RXD1 RXD2 RXD3 GND TXD0 TXD1 VDD TXD2 TXD3 TXEN100 nRWE0 RD7 RD6 RD5 RD4 GND RD3 RD2 RD1 VDD RD0 RD15 RD14
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
LAN91C110
144 Pin TQFP
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
A9 A8 A7 A6 A5 A4 A3 A2 A1 GND D8 D9 VDD D10 D11 D12 D13 D14 GND D15 nADS VDD RA16 RA14 RA15 RA9 RA10 RA8 RA11 VDD nROE RA7 GND RA13 RA6 RA5
SMSC DS - LAN91C110 REV. B
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 RA12 RA4 RA3 GND nRWE3 RA2 VDD RD24 RD25 RD26 RD27 RD28 RD29 GND nRWE2 RD30 RD31 VDD RD16 RD17 RD18 RD19 RD20 GND RD21 RD22 RD23 RD8 nRWE1 VDD RD9 RD10 RD11 GND RD12 RD13
FIGURE 1 - PIN CONFIGURATION
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TABLE 1 - DESCRIPTION OF PIN FUNCTIONS 144 TQFP NAME PIN NO. 115-112, Address 110-100 138 Address Enable 118, 117 SYMBOL A[15:1] AEN nBE[1:0] BUFFER TYPE I I I DESCRIPTION Input. Used by LAN91C110 for internal register selection. Input. Used as an address qualifier. Address decoding is only enabled when AEN is low. Input. Used during LAN91C110 register accesses to determine the width of the access and the register(s) being accessed. Bidirectional. 16-bit data bus used to access the LAN91C110's internal registers. Data bus has weak internal pullups. Supports direct connection to the system bus without external buffering. Input. This input is not considered active unless it is active for at least 100ns to filter narrow glitches. Open drain output. ARDY may be used when interfacing asynchronous buses to extend accesses. Its rising (access completion) edge is controlled by the XTAL1 clock and, therefore, asynchronous to the host CPU or bus clock. Note: Asserted for 100 to 150ns for the appropriate NO WAIT bit state in the Configuration register. See the NO WAIT bit description for complete information. Output. Local Device. This active low output is asserted when AEN is low and A4-A15 decode to the LAN91C110 address programmed into the high byte of the Base Address Register. nLDEV* is a combinatorial decode of unlatched address and AEN signals. Input. Address strobe. For systems that require address latching. The rising edge of nADS indicates the latching moment of A[1:15] and AEN. All LAN91C110 internal functions of A[1:15] and AEN are latched. Output. The interrupt output is enabled by selecting the appropriate routing bits (INT SEL 10) in the Configuration Register. Input. Used in asynchronous bus interfaces. Input. Used in asynchronous bus interfaces. Bidirectional. Carries the local buffer memory read and write data. Reads are always 32 bits wide. Writes are controlled individually at the byte level.
89, 91-95, Data Bus 97-98, 119, 121-123, 125-128 135 Reset 129
D[15:0]
I/O8
RESET
IS OD16
Asynchro- ARDY nous Ready
120
Local Device
nLDEV
O16
88
nAddress nADS Strobe
IS
131
Interrupt
INTR0
O4
132 134 56-57, 6065, 46-48, 50-54, 3538, 40-42, 45, 25-28, 30-32, 34
nRead nRD Strobe nWrite nWR Strobe RAM Data RD[31:0] Bus
IS IS I/O4 with pullups
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144 TQFP NAME PIN NO. 86,84,85, RAM 75,72,80, 82- Address 83,81, 77,74- Bus 73, 71-70,67 78 24,44,58, 68 2 3 Crystal 1 Crystal 2
SYMBOL RA[16:2]
BUFFER TYPE O4
DESCRIPTION Outputs. This bus specifies the buffer RAM doubleword being accessed by the LAN91C110.
nROE nRWE[3:0] XTAL1 XTAL2
1 139 23
nLink nLNK Status AUI Select AUISEL TXEN100
Transmit Enable MII 12 Carrier Sense MII 8 Receive Data Valid 11 Collision Detect MII 18,19,21, 22 Transmit Data 6 Transmit Clock 10 Receive Clock 16-13 Receive Data 141 Management Data Input 140 Management Data Output 137 Management Clock 7 Receive Error
Output. Active low signal used to read a doubleword from buffer RAM. O4 Outputs. Active low signals used to write any byte, word or dword in RAM. Iclk An external 25 MHz crystal is connected across these pins. If a TTL clock is supplied instead, it should be connected to XTAL1 and XTAL2 should be left open. I with pullup Input. General purpose input port used to convey LINK status (EPHSR bit 14). O4 Output. Non volatile output pin. Driven by AUI SELECT (CONFIG bit 8). O12 Output to MII PHY. Envelope to 100 Mbps transmission. I with pulldown I with pulldown I with pulldown O12 Input from MII PHY. Envelope of packet reception used for deferral and backoff purposes. Input from MII PHY. Envelope of data valid reception. Used for receive data framing. Input from MII PHY. Collision detection input. Outputs. Transmit Data nibble to MII PHY.
O4
CRS100 RX_DV COL100 TXD[3:0] TX25 RX25 RXD[3:0] MDI
I with pullup Input. Transmit clock input from MII. Nibble rate clock (25 MHz). I with pullup Input. Receive clock input from MII PHY. Nibble rate clock. I Inputs. Received Data nibble from MII PHY. I with pulldown O4 MII management data input.
MDO
MII management data output.
MCLK
O4
MII management clock.
RX_ER
I with pulldown
Input. Indicates a code error detected by PHY. Used by the LAN91C110 to discard the packet being received. The error indication reported for this event is the same as a bad CRC (Receive Status Word bit 13).
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144 TQFP NAME PIN NO. 5 nChip Select Output 4,20,33,43,5 Power 5,66,79, 87,96,111,13 3 144 Analog Power 9,17,29,39,4 Ground 9,59,69, 76,90,99, 116,124, 130,136, 142 Analog Ground
SYMBOL nCSOUT
BUFFER TYPE O4
DESCRIPTION Output. Chip Select provided for mapping of PHY functions into LAN91C110 decoded space. Active on accesses to LAN91C110's eight lower addresses when the BANK SELECTED is 7. +5V power supply pins.
VDD
AVDD GND
+5V analog power supply pins. Ground pins.
AGND
Analog ground pin.
TABLE 2 - BUFFER TYPES O4 O12 OD16 I/O4 I/O8 IS I with pullup I with pulldown Output buffer with 2mA source and 4mA sink Output buffer with 6mA source and 12mA sink Open drain buffer with 16mA sink Bidirectional buffer with 2mA source and 4mA sink Bidirectional buffer with 4mA source and 8mA sink Schmitt Trigger (Hysteresis: 250mV) Rated at 30mA Rated at 30mA
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Address Data Control BUS INTERFACE UNIT
ARBITER
DIRECT MEMORY ACCESS MEDIA ACCESS CONTROL
MEMORY MANAGEMENT UNIT
10/100 Mb/s Media Independent Interface
RD FIFO
WR FIFO
RAM
25 MHz
FIGURE 2 - LAN91C110 BLOCK DIAGRAM
SYSTEM BUS
ADDRESS
ADDRESS
CONTROL
CONTROL
DATA
DATA
LAN91C110 FEAST
MII OE,WE RD0-31 OR
100BASE-T4 INTERFACE CHIP
100BASE-T4
RA
SRAM 32kx8 1
2
34
100BASE-TX INTERFACE LOGIC/ 10BASE-T
100BASE-TX/ 10BASE-T
FIGURE 3 - LAN91C110 SYSTEM DIAGRAM
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FUNCTIONAL DESCRIPTION
DESCRIPTION OF BLOCKS Clock Generator Block 1. 2. The XTAL1 and XTAL2 pins are to be connected to a 25 MHz 50 PPM crystal. TX25 is an input clock. It will be the nibble rate of the particular PHY connected to the MII (2.5 MHz for a 10 Mbps PHY, and 25 MHz for a 100 Mbps PHY). RX25 - This is the MII nibble rate receive clock used for sampling received data nibbles and running the receive state machine. (2.5 MHz for a 10 Mbps PHY, and 25 MHz for a 100 Mbps PHY).
3.
CSMA/CD BLOCK This is a 16 bit oriented block, with fully- independent Transmit and Receive logic. The data path in and out of the block consists of two 16-bit wide uni-directional FIFOs interfacing the DMA block. The DMA port of the FIFO stores 32 bits to exploit the 32 bit data path into memory, but the FIFOs themselves are 16 bit wide. The Control Path consists of a set of registers interfaced to the CPU via the BIU. DMA Block This block accesses packet memory on the CSMA/CD's behalf, fetching transmit data and storing received data. It interfaces the CSMA/CD Transmit and Receive FIFOs on one side, and the Arbiter block on the other. To increase the bandwidth into memory, a 50 MHz clock is used by the DMA block, and the data path is 32 bits wide. For example, during active reception at 100 Mbps, the CSMA/CD block will write a word into the Receive FIFO every 160ns. The DMA will read the FIFO and accumulate two words on the output port to request a memory cycle from the Arbiter every 320ns. The DMA machine is able to support full duplex operation. Independent receive and transmit counters are used. Transmit and receive cycles are alternated when simultaneous receive and transmit accesses are needed. Arbiter Block The Arbiter block sequences accesses to packet RAM requested by the BIU and by the DMA blocks. BIU requests represent pipelined CPU accesses to the Data Register, while DMA requests represent CSMA/CD data movement. The external memory used is a 25ns SRAM. The Arbiter is also responsible for controlling the nRWE0-nRWE3 lines as a function of the bytes being written. Read accesses are always 32 bit wide, and the Arbiter steers the appropriate byte(s) to the appropriate lanes as a function of the address. The CPU Data Path consists of two uni-directional FIFOs mapped at the Data Register location. These FIFOs can be accessed in any combination of bytes, word, or doublewords. The Arbiter will indicate 'Not Ready' whenever a cycle is initiated that cannot be satisfied by the present state of the FIFO.
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MMU Block The Hardware Memory Management Unit allocates memory and transmit and receive packet queues. It also determines the value of the transmit and receive interrupts as a function of the queues. The page size is 2k, with a maximum memory size of 128k. MIR and MCR values are interpreted in 512 byte units. BIU Block The Bus Interface Unit can handle synchronous as well as asynchronous buses; different signals are used for each one. Transparent latches are added on the address path using rising nADS for latching. With ISA, the read and write operations are controlled by the edges of nRD and nWR. ARDY is used for notifying the system that it should extend the access cycle. The leading edge of ARDY is generated by the leading edge of nRD or nWR while the trailing edge of ARDY is controlled by the internal LAN91C110 clock and, therefore, asynchronous to the bus. The BIU is implemented using the following principles: 1. 2. 3. 4. 5. 6. Address decoding is based on the values of A15-A4 and AEN. Address latching is performed by using transparent latches that are transparent when nADS=0 and nRD=1, nWR=1 and latch on nADS rising edge. Byte, word and doubleword accesses to all registers and Data Path are supported except a doubleword write to offset Ch will only write the BANK SELECT REGISTER (offset Fh). No bus byte swapping is implemented (no eight bit mode). Word swapping as a function of A1 is implemented for 16 bit bus support. The asynchronous interface uses nRD and nWR strobes. If necessary, ARDY is negated on the leading edge of the strobe. The ARDY trailing edge is controlled by CLK.
MAC-PHY Interface Block For the MII interface, transmit data is clocked out using the TX25 clock input, while receive data is clocked in using RX25. In 100 Mbps mode, the LAN91C110 provides the following interface signals to the PHY: For transmission: TXEN100 TXD0-3 TX25 For reception: RX_DV RX_ER RXD0-3 RX25 For CSMA/CD state machines: CRS100 COL100 A transmission begins by TXEN100 going active (high), and TXD0-TXD3 having the first valid preamble nibble. TXD0 carries the least significant bit of the nibble (that is the one that would go first out of the EPH at 100 Mbps), while TXD3 carries the most significant bit of the nibble. TXEN100 and TXD0-TXD3 are clocked by the LAN91C110 using TX25 rising edges. TXEN100 goes inactive at the end of the packet on the last nibble of the CRC. During a transmission, COL100 might become active to indicate a collision. COL100 is asynchronous to the LAN91C110's clocks and will be synchronized internally to TX25. Reception begins when RX_DV (receive data valid) is asserted. A preamble pattern or flag octet will be present at RXD0RXD3 when RX_DV is activated. The LAN91C110 requires no training sequence beyond a full flag octet for reception. RX_DV as well as RXD0-RXD3 are sampled on RX25 rising edges. RXD0 carries the least significant bit and RXD3 the most significant bit of the nibble. RX_DV goes inactive when the last valid nibble of the packet (CRC) is presented at RXD0-RXD3.
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RX_ER might be asserted during packet reception to signal the LAN91C110 that the present receive packet is invalid. The LAN91C110 will discard the packet by treating it as a CRC error. RXD0-RXD3 should always be aligned to packet nibbles, therefore, opening flag detection does not consider misaligned cases. Opening flag detection expects the 5Dh pattern and will not reject the packet on non-preamble patterns. CRS100 is used as a frame envelope signal for the CSMA/CD MAC state machines (deferral and backoff functions), but it is not used for receive framing functions. CRS100 is an asynchronous signal and it will be active whenever there is activity on the cable, including LAN91C110 transmissions and collisions. The MII SELECT bit in the CONFIG REGISTER must always be set for proper chip function. Note that given the modular nature of the MII, TX25 and RX25 cannot be assumed to be free running clocks. The LAN91C110 will not rely on the presence of TX25 and RX25 during reset and will use its own internal clock whenever a timeout on TX25 is detected. MII Management Interface Block PHY management through the MII management interface is supported by the LAN91C110 by providing the means to drive a tri-statable data output, a clock, and reading an input. Timing and framing for each management command is to be generated by the CPU.
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EEPROM INTERFACE
Control Control
Control
Control
Control
Arbiter
Control
Address
8-16 bit Bus Interface Unit
Control
MMU
TX/RX FIFO Pointer
DMA
Ethernet Protocol Handler (EPH)
WR FIFO
Data
TX Data
TXD[0-3]
RD FIFO
32-bit Data 32-bit Data
RX Data
RXD[0-3]
External SRAM
FIGURE 4 - LAN91C110 INTERNAL BLOCK DIAGRAM WITH DATAPATH
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DATA STRUCTURES AND REGISTERS
PACKET FORMAT IN BUFFER MEMORY
The packet format in memory is similar for the Transmit and Receive areas. The first word is reserved for the status word. The next word is used to specify the total number of bytes, and it is followed by the data area. The data area holds the packet itself.
RAM OFFSET (DECIMAL) 0 2 4
bit15 2nd Byte STATUS WORD RESERVED BYTE COUNT (always even) 1st Byte
bit0
DATA AREA
2046 Max CONTROL BYTE Last Byte
LAST DATA BYTE (if odd)
FIGURE 5 - DATA PACKET FORMAT
TRANSMIT PACKET
STATUS WORD BYTE COUNT DATA AREA CONTROL BYTE Written by CSMA upon transmit completion (see Status Register) Written by CPU Written/modified by CPU Written by CPU to control odd/even data bytes
RECEIVE PACKET
Written by CSMA upon receive completion (see RX Frame Status Word) Written by CSMA Written by CSMA Written by CSMA; also has odd/even bit
BYTE COUNT - Divided by two, it defines the total number of words including the STATUS WORD, the BYTE COUNT WORD, the DATA AREA and the CONTROL BYTE. The receive byte count always appears as even; the ODDFRM bit of the receive status word indicates if the low byte of the last word is relevant.
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The transmit byte count least significant bit will be assumed 0 by the controller regardless of the value written in memory. DATA AREA - The data area starts at offset 4 of the packet structure and can extend up to 2043 bytes. The data area contains six bytes of DESTINATION ADDRESS followed by six bytes of SOURCE ADDRESS, followed by a variable-length number of bytes. On transmit, all bytes are provided by the CPU, including the source address. The LAN91C110 does not insert its own source address. On receive, all bytes are provided by the CSMA side. The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by the LAN91C110. It is treated transparently as data both for transmit and receive operations. CONTROL BYTE - For transmit packets the CONTROL BYTE is written by the CPU as: X X ODD CRC 0 0 0 0
ODD - If set, indicates an odd number of bytes, with the last byte being right before the CONTROL BYTE. If clear, the number of data bytes is even and the byte before the CONTROL BYTE is not transmitted. CRC - When set, CRC will be appended to the frame. This bit has only meaning if the NOCRC bit in the TCR is set. For receive packets the CONTROL BYTE is written by the controller as: 0 1 ODD 0 0 0 0 0
ODD - If set, indicates an odd number of bytes, with the last byte being right before the CONTROL BYTE. If clear, the number of data bytes is even and the byte before the CONTROL BYTE should be ignored.
RECEIVE FRAME STATUS WORD
This word is written at the beginning of each receive frame in memory. It is not available as a register. HIGH BYTE LOW BYTE 5 4 ALGN ERR BROD CAST BAD CRC ODD FRM TOOLNG TOO SHORT MULT CAST 1 0
HASH VALUE 3 2
ALGNERR - Frame had alignment error. When MII SEL=1 alignment error is set when BADCRC=1 and an odd number of nibbles was received between SFD and RX_DV going inactive. BRODCAST - Receive frame was broadcast. BADCRC - Frame had CRC error, or RX_ER was asserted during reception.
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ODDFRM - This bit when set indicates that the received frame had an odd number of bytes. TOOLNG - Frame length was longer than 802.3 maximum size (1518 bytes on the cable). TOOSHORT - Frame length was shorter than 802.3 minimum size (64 bytes on the cable). HASH VALUE - Provides the hash value used to index the Multicast Registers. Can be used by receive routines to speed up the group address search. The hash value consists of the six most significant bits of the CRC calculated on the Destination Address, and maps into the 64 bit multicast table. Bits 5,4,3 of the hash value select a byte of the multicast table, while bits 2,1,0 determine the bit within the byte selected. Examples of the address mapping:
ADDRESS ED 00 00 00 00 00 0D 00 00 00 00 00 01 00 00 00 00 00 2F 00 00 00 00 00
HASH VALUE 5-0 000 000 010 000 100 111 111 111
MULTICAST TABLE BIT MT-0 bit 0 MT-2 bit 0 MT-4 bit 7 MT-7 bit 7
MULTCAST - Receive frame was multicast. If hash value corresponds to a multicast table bit that is set, and the address was a multicast, the packet will pass address filtering regardless of other filtering criteria.
I/O SPACE
The base I/O space is specified by the power-up I/O Base Register default. To limit the I/O space requirements to 16 locations, the registers are assigned to different banks. The last word of the I/O area is shared by all banks and can be used to change the bank in use. Registers are described using the following convention:
OFFSET
HIGH BYTE bit 15 X LOW BYTE bit 7 X bit 14 X bit 6 X
NAME
bit 13 X bit 5 X bit 12 X bit 4 X
TYPE
bit 11 X bit 3 X bit 10 X bit 2 X
SYMBOL
bit 9 X bit 1 X bit 8 X bit 0 X
OFFSET - Defines the address offset within the IOBASE where the register can be accessed at, provided the bank select has the appropriate value. The offset specifies the address of the even byte (bits 0-7) or the address of the complete word. The odd byte can be accessed using address (offset + 1). Some registers (like the Interrupt Ack., or like Interrupt Mask) are functionally described as two eight bit registers, in that case the offset of each one is independently specified. Regardless of the functional description, all registers can be accessed as doublewords, words or bytes. The default bit values upon hard reset are highlighted below each register.
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TABLE 3 - INTERNAL I/O SPACE MAPPING
0 2 4 6 8 A C E
BANK0 TCR EPH STATUS RCR COUNTER MIR MCR RESERVED (0) BANK SELECT
BANK1 CONFIG BASE IA0-1 IA2-3 IA4-5 CONTROL BANK SELECT
BANK2 MMU COMMAND PNR FIFO PORTS POINTER DATA DATA INTERRUPT BANK SELECT
BANK3 MT0-1 MT2-3 MT4-5 MT6-7 MGMT REVISION ERCV BANK SELECT
A special BANK (BANK7) exists to support the addition of external registers.
BANK SELECT REGISTER OFFSET E NAME BANK SELECT REGISTER TYPE READ/WRITE SYMBOL BSR
HIGH BYTE
0 0
0 0
1 1
1 1
0 0
0 0 BS2
1 1 BS1 0
1 1 BS0 0
LOW BYTE X X X X X
0
BS2, BS1, BS0 Determine the bank presently in use. This register is always accessible and is used to select the register bank in use. The upper byte always reads as 33h and can be used to help determine the I/O location of the LAN91C110. The BANK SELECT REGISTER is always accessible regardless of the value of BS0-2.
Note: The bank select register can be accessed as a word at offset 0x0Eh, or as a byte at offset 0x0Fh. BANK 7 has no internal registers other than the BANK SELECT REGISTER itself. On valid cycles where BANK7 is selected (BS0=BS1=BS2=1), and A3=0, nCSOUT is activated to facilitate implementation of external registers. Note: BANK7 does not exist in LAN91C9x devices. For backward S/W compatibility BANK7 accesses should be done if the Revision Control register indicates the device is the LAN91C110.
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BANK 0 OFFSET 0 NAME TRANSMIT CONTROL REGISTER TYPE READ/WRITE SYMBOL TCR
This register holds bits programmed by the CPU to control some of the protocol transmit options. HIGH BYTE LOW BYTE SWFDUP 0 PAD_EN 0 Reserved 0 Reserved 0 EPH LOOP 0 Reserved 0 STP SQET 0 Reserved 0 FDUPLX 0 Reserved 0 Reserved 0 FORCOL 0 Reserved 0 Reserved 0 NOCRC 0 TXENA 0
SWFDUP - Enables Switched Full Duplex mode. In this mode, transmit state machine is inhibited from recognizing carrier sense, so deferrals will not occur. Also inhibits collision count, therefore, the collision related status bits in the EPHSR are not valid (CTR_ROL, LATCOL, SQET, 16COL, MUL COL, and SNGL COL). Uses COL100 as flow control, limiting backoff and jam to 1 clock each before inter-frame gap, then retry will occur after IFG. If COL100 is active during preamble, full preamble will be output before jam. When SWFDUP is high, the values of FDUPLX and MON_CSN have no effect. This bit should be low for non-MII operation. EPH_LOOP - Internal loopback at the EPH block. Serial data is internally looped back when set. Defaults low. When EPH_LOOP is high the following transmit outputs are forced inactive: TXD0-TXD3 = 0h, TXEN100 = TXEN = 0, TXD = 1. The following and external inputs are blocked: CRS=CRS100=0, COL=COL100=0, RX_DV= RX_ER=0. STP_SQET - Stop transmission on SQET error. If set, stops and disables transmitter on SQE test error. Does not stop on SQET error and transmits next frame if clear. Defaults low. FDUPLX - When set the LAN91C110 will cause frames to be received if they pass the address filter regardless of the source for the frame. When clear the node will not receive a frame sourced by itself. This bit does not control the duplex mode operation, the duplex mode operation is controlled by the SWFDUP bit. NOCRC - Does not append CRC to transmitted frames when set. Allows software to insert the desired CRC. Defaults to zero, namely CRC inserted. PAD_EN - When set, the LAN91C110 will pad transmit frames shorter than 64 bytes with 00. For TX, CPU should write the actual BYTE COUNT before padded by the LAN91C110 to the buffer RAM, excludes the padded 00. When this bit is cleared, the LAN91C110 does not pad frames. FORCOL - When set, the FORCOL bit will force a collision by not deferring deliberately. This bit is set and cleared only by the CPU. When TXENA is enabled with no packets in the queue and while the FORCOL bit is set, the LAN91C110 will transmit a preamble pattern the next time a carrier is seen on the line. If a packet is queued, a preamble and SFD will be transmitted. This bit defaults low to normal operation. NOTE: The LATCOL bit in the EPHSR, setting up as a result of FORCOL, will reset TXENA to 0. In order to force another collision, TXENA must be set to 1 again. TXENA - Transmit enabled when set. Transmit is disabled if clear. When the bit is cleared the LAN91C110 will complete the current transmission before stopping. When stopping due to an error, this bit is automatically cleared.
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BANK 0 OFFSET 2 NAME EPH STATUS REGISTER TYPE READ ONLY SYMBOL EPHSR
This register stores the status of the last transmitted frame. This register value, upon individual transmit packet completion, is stored as the first word in the memory area allocated to the packet. Packet interrupt processing should use the copy in memory as the register itself will be updated by subsequent packet transmissions. The register can be used for real time values (like TXENA and LINK OK). If TXENA is cleared the register holds the last packet completion status. HIGH BYTE TX UNRN 0 LOW BYTE TX DEFR 0 LINK_ OK -nLNK pin LTX BRD 0 Reserved 0 CTR _ROL 0 EXC _DEF 0 LTX MULT 0
Reserved 0 MUL COL 0
LATCOL 0 SNGL COL 0
Reserved 0
SQET 0
16COL 0
TX_SUC 0
TXUNRN - Transmit Under Run. Set if under run occurs, it also clears TXENA bit in TCR. Cleared by setting TXENA high. This bit may only be set if early TX is being used. LINK_OK - General purpose input port driven by nLNK pin inverted. Typically used for Link Test. A transition on the value of this bit generates an interrupt. CTR_ROL - Counter Roll Over. When set one or more 4 bit counters have reached maximum count (15). Cleared by reading the ECR register. EXC_DEF - Excessive Deferral. When set last/ current transmit was deferred for more than 1518 * 2 byte times. Cleared at the end of every packet sent. LATCOL - Late collision detected on last transmit frame. If set a late collision was detected (later than 64 byte times into the frame). When detected the transmitter jams and turns itself off clearing the TXENA bit in TCR. Cleared by setting TXENA in TCR. TX_DEFR - Transmit Deferred. When set, carrier was detected during the first 6.4 s of the inter frame gap. Cleared at the end of every packet sent. LTX_BRD - Last transmit frame was a broadcast. Set if frame was broadcast. Cleared at the start of every transmit frame. SQET - Signal Quality Error Test. SQET bit is always set after first transmit, except if SWFDUP=1. As a consequence, the STP_SQET bit in the TCR register cannot be set as it will always result in transmit fatal error. Transmission stops and EPH INT is set if STP_SQET is in the TCR is also set when SQET is set. This bit is cleared by setting TXENA high. 16COL - 16 collisions reached. Set when 16 collisions are detected for a transmit frame. TXENA bit in TCR is reset. Cleared when TXENA is set high. LTX_MULT - Last transmit frame was a multicast. Set if frame was a multicast. Cleared at the start of every transmit frame.
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MULCOL - Multiple collision detected for the last transmit frame. Set when more than one collision was experienced. Cleared when TX_SUC is high at the end of the packet being sent. SNGLCOL - Single collision detected for the last transmit frame. Set when a collision is detected. Cleared when TX_SUC is high at the end of the packet being sent. TX_SUC - Last transmit was successful. Set if transmit completes without a fatal error. This bit is cleared by the start of a new frame transmission or when TXENA is set high. Fatal errors are: 16 collisions (1/2 duplex mode only) SQET fail and STP_SQET = 1 (1/2 duplex mode only) FIFO Underrun Late collision (1/2 duplex mode only)
BANK 0 OFFSET 4
HIGH BYTE SOFT RST 0 LOW BYTE Reserved 0
NAME RECEIVE CONTROL REGISTER
FILT CAR 0 Reserved 0 ABORT_E NB 0 Reserved 0 Reserved 0 Reserved 0
TYPE READ/WRITE
Reserved 0 Reserved 0 Reserved 0 ALMUL 0
SYMBOL RCR
STRIP CRC 0 PRMS 0 RXEN 0 RX_ ABORT 0
SOFT_RST - Software-Activated Reset. Active high. Initiated by writing this bit high and terminated by writing the bit low. The LAN91C110's configuration is not preserved except for Configuration, Base, and IA0-IA5 Registers. EEPROM is not reloaded after software reset. FILT_CAR - Filter Carrier. When set filters leading edge of carrier sense for 12 bit times (3 nibble times). Otherwise recognizes a receive frame as soon as carrier sense is active. (Does NOT filter RX DV on MII!) ABORT_ENB - Enables abort of receive when collision occurs. Defaults low. When set, the LAN91C110 will automatically abort a packet being received when the appropriate collision input is This bit has no effect if the SWFDUP bit in the TCR is set. STRIP_CRC - When set it strips the CRC on received frames. When clear the CRC is stored in memory following the packet. Defaults low. RXEN - Enables the receiver when set. If cleared, completes receiving current frame and then goes idle. Defaults low on reset. ALMUL - When set accepts all multicast frames (frames in which the first bit of DA is '1'). When clear accepts only the multicast frames that match the multicast table setting. Defaults low. PRMS - Promiscuous mode. When set receives all frames. Does not receive its own transmission unless it is in Full Duplex!
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RX_ABORT - This bit is set if a receive frame was aborted due to length longer than 2K bytes. The frame will not be received. The bit is cleared by RESET or by the CPU writing it low. Reserved - Must be 0.
BANK 0 OFFSET 6 NAME COUNTER REGISTER TYPE READ ONLY SYMBOL ECR
Counts four parameters for MAC statistics. When any counter reaches 15 an interrupt is issued. All counters are cleared when reading the register and do not wrap around beyond 15. HIGH BYTE NUMBER OF EXC. DEFFERED TX 0 LOW BYTE 0 0 0 0 0 NUMBER OF DEFFERED TX 0 0 0
MULTIPLE COLLISION COUNT 0 0 0 0
SINGLE COLLISION COUNT 0 0 0
Each four bit counter is incremented every time the corresponding event, as defined in the EPH STATUS REGISTER bit description, occurs. Note that the counters can only increment once per enqueued transmit packet, never faster, limiting the rate of interrupts that can be generated by the counters. For example if a packet is successfully transmitted after one collision the SINGLE COLLISION COUNT field is incremented by one. If a packet experiences between 2 to 16 collisions, the MULTIPLE COLLISION COUNT field is incremented by one. If a packet experiences deferral the NUMBER OF DEFERRED TX field is incremented by one, even if the packet experienced multiple deferrals during its collision retries. The COUNTER REGISTER facilitates maintaining statistics in the AUTO RELEASE mode where no transmit interrupts are generated on successful transmissions. Reading the register in the transmit service routine will be enough to maintain statistics.
BANK 0 OFFSET 8
HIGH BYTE 1 LOW BYTE 1 1 1
NAME MEMORY INFORMATION REGISTER
TYPE READ ONLY
SYMBOL MIR
FREE MEMORY AVAILABLE (IN BYTES * 256 * M) 1 1 1 1 1 1
MEMORY SIZE (IN BYTES *256 * M) 1 1 1 1 1 1
FREE MEMORY AVAILABLE - This register can be read at any time to determine the amount of free memory. The register defaults to the MEMORY SIZE upon reset or upon the RESET MMU command. MEMORY SIZE - This register can be read to determine the total memory size.
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All memory related information is represented in 256 * M byte units, where the multiplier M is determined by the MCR upper byte. These register default to FFh, which should be interpreted as 256.
BANK 0 OFFSET A NAME MEMORY CONFIGURATION REGISTER TYPE Lower Byte READ/WRITE Upper Byte READ ONLY SYMBOL MCR
HIGH BYTE 0 LOW BYTE 0 0 1 1
MEMORY SIZE MULTIPLIER 0 1 0 1
MEMORY RESERVED FOR TRANSMIT (IN BYTES * 256 * M) 0 0 0 0 0 0 0
MEMORY RESERVED FOR TRANSMIT - Programming this value allows the host CPU to reserve memory to be used later for transmit, limiting the amount of memory that receive packets can use. When programmed for zero, the memory allocation between transmit and receive is completely dynamic. When programmed for a non-zero value, the allocation is dynamic if the free memory exceeds the programmed value, while receive allocation requests are denied if the free memory is less or equal to the programmed value. This register defaults to zero upon reset. It is not affected by the RESET MMU command. The value written to the MCR is a reserved memory space IN ADDITION TO ANY MEMORY CURRENTLY IN USE. If the memory allocated for transmit plus the reserved space for transmit is required to be constant (rather than grow with transmit allocations) the CPU should update the value of this register after allocating or releasing memory. The contents of the MIR as well as the low byte of the MCR are specified in units of 256 * M bytes, where M is the Memory Size Multiplier. M=2 for the LAN91C110. A value of 04h in the lower byte of the MCR is equal to one 2K page (4 * 256 *2 = 2K); since memory must be reserved in multiples of pages, bits 0 and 1 of the MCR should be written to 1 only when the entire memory is being reserved for transmit (i.e., low byte of MCR = FFh).
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BANK1 OFFSET 0 NAME CONFIGURATION REGISTER TYPE READ/WRITE SYMBOL CR
The Configuration Register holds bits that define the adapter configuration and are not expected to change during runtime. This register is part of the EEPROM saved setup. HIGH BYTE MII SELECT 1 LOW BYTE 1 1 Reserved 0 Reserved 0 1 1 NO WAIT 0 Reserved 1 0 Reserved 0 FULL STEP 0 INT SEL1 0 Reserved 0 INT SEL0 0 1 AUI SELECT 0
MII SELECT - Used to select the network interface port. When set, the LAN91C110 will use its MII port and interface a PHY device at the nibble rate. This bit must always be set for proper chip function. NO WAIT - When set, does not request additional wait states. An exception to this are accesses to the Data Register if not ready for a transfer. When clear, negates ARDY for two to three clocks on any cycle to the LAN91C110. FULL STEP - Reserved AUI SELECT - This bit is a general purpose output port. Its value drives pin AUISEL and can be used as a general purpose non-volatile configuration pin. Defaults low. Reserved - Must be 0. INT SEL1-0 - Used to select interrupt pin. The bits must remain 00 for the interrupt pin to be asserted for interrupt indication. All other bit combinations are undefined.
BANK 1 OFFSET 2 NAME BASE ADDRESS REGISTER TYPE READ/WRITE SYMBOL BAR
This register holds the I/O address decode option chosen for the LAN91C110. Is not usually modified during run-time. HIGH BYTE A15 0 LOW BYTE 0 0 0 A14 0 A13 0 A9 1 Reserved 0 0 0 0 A8 1 A7 0 A6 0 A5 0 1 1
A15 - A13 and A9 - A5 - These bits are compared against the I/O address on the bus to determine the IOBASE for the LAN91C110`s registers. The 64k I/O space is fully decoded by the LAN91C110 down to a 16 location space, therefore the unspecified address lines A4, A10, A11 and A12 must be all zeros.
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The I/O base decode defaults to 300h (namely, the high byte defaults to 18h). Reserved - Must be 0.
BANK 1 OFFSET 4 THROUGH 9 NAME INDIVIDUAL ADDRESS REGISTERS TYPE READ/WRITE SYMBOL IAR
These registers are required to be written by the host following power-up and hardware reset. For PC Card designs, the CIS contains the node address. The S/W driver must load that address into these registers. The registers are modified by the software driver. Bit 0 of Individual Address 0 register corresponds to the first bit of the address on the cable. LOW BYTE 0 HIGH BYTE 0 LOW BYTE 0 HIGH BYTE 0 LOW BYTE 0 HIGH BYTE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS 0 0 0 0 0 0
ADDRESS 1
ADDRESS 2 0 0 0 0 0
ADDRESS 3
ADDRESS 4 0 0 0 0 0
ADDRESS 5
BANK 1 OFFSET A
Reserved.
NAME
TYPE
SYMBOL
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BANK 1 OFFSET C
HIGH BYTE
NAME CONTROL REGISTER
Reserved 0 RCV_ BAD 0 CR ENABLE 0 Reserved 0 TE ENABLE 0 1 1 1 1
TYPE READ/WRITE
AUTO RELEASE 0 Reserved 0 Reserved 0 Reserved 0
SYMBOL CTR
1 1 Reserved 0 Reserved 0 Reserved 0
LOW BYTE
LE ENABLE 0
RCV_BAD - When set, bad CRC packets are received. When clear bad CRC packets do not generate interrupts and their memory is released. AUTO RELEASE - When set, transmit pages are released by transmit completion if the transmission was successful (when TX_SUC is set). In that case there is no status word associated with its packet number, and successful packet numbers are not even written into the TX COMPLETION FIFO. A sequence of transmit packets will generate an interrupt only when the sequence is completely transmitted (TX EMPTY INT will be set), or when a packet in the sequence experiences a fatal error (TX INT will be set). Upon a fatal error TXENA is cleared and the transmission sequence stops. The packet number that failed, is present in the FIFO PORTS register, and its pages are not released, allowing the CPU to restart the sequence after corrective action is taken. LE ENABLE - Link Error Enable. When set it enables the LINK_OK bit transition as one of the interrupts merged into the EPH INT bit. Clearing the LE ENABLE bit after an EPH INT interrupt, caused by a LINK_OK transition, will acknowledge the interrupt. LE ENABLE defaults low (disabled). CR ENABLE - Counter Roll over Enable. When set, it enables the CTR_ROL bit as one of the interrupts merged into the EPH INT bit. Reading the COUNTER register after an EPH INT interrupt caused by a counter rollover, will acknowledge the interrupt. CR ENABLE defaults low (disabled). TE ENABLE - Transmit Error Enable. When set it enables Transmit Error as one of the interrupts merged into the EPH INT bit. An EPH INT interrupt caused by a transmitter error is acknowledged by setting TXENA bit in the TCR register to 1 or by clearing the TE ENABLE bit. TE ENABLE defaults low (disabled). Transmit Error is any condition that clears TXENA with TX_SUC staying low as described in the EPHSR register. Reserved 2-0: These reserved bits must always be written to as zero(0).
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BANK2 OFFSET 0 NAME MMU COMMAND REGISTER TYPE WRITE ONLY BUSY Bit Readable SYMBOL MMUCR
This register is used by the CPU to control the memory allocation, de-allocation, TX FIFO and RX FIFO control. The three command bits determine the command issued as described below: HIGH BYTE
LOW BYTE X
COMMAND Y Z
Reserved
Reserved
N2
N1
N0/BUSY
0
COMMAND SET:
xyz 000 001 0) 1) NOOP - NO OPERATION ALLOCATE MEMORY FOR TX - N2, N1, N0 defines the amount of memory requested as (value + 1) * 256 bytes. Namely N2, N1, N0 = 1 will request 2 * 256 = 512 bytes. A shift-based divide by 256 of the packet length yields the appropriate value to be used as N2, N1, N0. Immediately generates a completion code at the ALLOCATION RESULT REGISTER. Can optionally generate an interrupt on successful completion. N2, N1, N0 are ignored by the LAN91C110 but should be implemented in LAN91C110 software drivers for LAN9000 compatibility. RESET MMU TO INITIAL STATE - Frees all memory allocations, clears relevant interrupts, resets packet FIFO pointers. REMOVE FRAME FROM TOP OF RX FIFO - To be issued after CPU has completed processing of present receive frame. This command removes the receive packet number from the RX FIFO and brings the next receive frame (if any) to the RX area (output of RX FIFO). REMOVE AND RELEASE TOP OF RX FIFO - Like 3) but also releases all memory used by the packet presently at the RX FIFO output. The MMU busy time after issuing REMOVE and RELEASE command depends on the time when the busy bit is cleared. The time from issuing REMOVE and RELEASE command on the last receive packet to the time when receive FIFO is empty depends on RX INT bit turning low. An alternate approach can be checking the read RX FIFO register. RELEASE SPECIFIC PACKET - Frees all pages allocated to the packet specified in the PACKET NUMBER REGISTER. Should not be used for frames pending transmission. Typically used to remove transmitted frames, after reading their completion status. Can be used following 3) to release receive packet memory in a more flexible way than 4). ENQUEUE PACKET NUMBER INTO TX FIFO - This is the normal method of transmitting a packet just loaded into RAM. The packet number to be enqueued is taken from the PACKET NUMBER REGISTER. RESET TX FIFOs - This command will reset both TX FIFOs: The TX FIFO holding the packet numbers awaiting transmission and the TX Completion FIFO. This command provides a mechanism for canceling packet transmissions, and reordering or bypassing the transmit queue. The RESET TX FIFOs command should only be used when the transmitter is disabled. Unlike the RESET MMU command, the RESET TX FIFOs does not release any memory.
010 011
2) 3)
100
4)
101
5)
110 111
6) 7)
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Note 1: Bits N2,N1,N0 bits are ignored by the LAN91C110 but should be used for command 0 to preserve software compatibility with the LAN91C92 and future devices. They should be zero for all other commands. Note 2: When using the RESET TX FIFOS command, the CPU is responsible for releasing the memory associated with outstanding packets, or re-enqueuing them. Packet numbers in the completion FIFO can be read via the FIFO ports register before issuing the command. Note 3: MMU commands releasing memory (commands 4 and 5) should only be issued if the corresponding packet number has memory allocated to it. COMMAND SEQUENCING
A second allocate command (command 1) should not be issued until the present one has completed. Completion is determined by reading the FAILED bit of the allocation result register or through the allocation interrupt. A second release command (commands 4, 5) should not be issued if the previous one is still being processed. The BUSY bit indicates that a release command is in progress. After issuing command 5, the contents of the PNR should not be changed until BUSY goes low. After issuing command 4, command 3 should not be issued until BUSY goes low. BUSY BIT - Readable at bit 0 of the MMU command register address. When set indicates that MMU is still processing a release command. When clear, MMU has already completed last release command. BUSY and FAILED bits are set upon the trailing edge of command.
BANK 2 OFFSET 2
Reserved 0
NAME PACKET NUMBER REGISTER
Reserved 0 0 0
TYPE READ/WRITE
SYMBOL PNR
PACKET NUMBER AT TX AREA 0 0 0 0
PACKET NUMBER AT TX AREA - The value written into this register determines which packet number is accessible through the TX area. Some MMU commands use the number stored in this register as the packet number parameter. This register is cleared by a RESET or a RESET MMU Command.
OFFSET 3
NAME ALLOCATION RESULT REGISTER
TYPE READ ONLY
SYMBOL ARR
This register is updated upon an ALLOCATE MEMORY MMU command. FAILED 1 Reserved 0 0 0 ALLOCATED PACKET NUMBER 0 0 0 0
FAILED - A zero indicates a successful allocation completion. If the allocation fails the bit is set and only cleared when the pending allocation is satisfied. Defaults high upon reset and reset MMU command. For polling purposes, the ALLOC_INT in the Interrupt Status Register should be used because it is synchronized to the read operation. Sequence:
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1. Allocate Command 2. Poll ALLOC_INT bit until set 3. Read Allocation Result Register ALLOCATED PACKET NUMBER - Packet number associated with the last memory allocation request. The value is only valid if the FAILED bit is clear.
Note: For software compatibility with future versions, the value read from the ARR after an allocation request is intended to be written into the PNR as is, without masking higher bits (provided FAILED = 0). BANK 2 OFFSET 4 NAME FIFO PORTS REGISTER TYPE READ ONLY SYMBOL FIFO
This register provides access to the read ports of the Receive FIFO and the Transmit completion FIFO. The packet numbers to be processed by the interrupt service routines are read from this register. HIGH BYTE REMPTY 1 LOW BYTE TEMPTY 1 0 0 0 0 0 0 0 0 RX FIFO PACKET NUMBER 0 0 0 0
TX FIFO PACKET NUMBER 0 0 0 0
REMPTY - No receive packets queued in the RX FIFO. For polling purposes, uses the RCV_INT bit in the Interrupt Status Register. TOP OF RX FIFO PACKET NUMBER - Packet number presently at the output of the RX FIFO. Only valid if REMPTY is clear. The packet is removed from the RX FIFO using MMU Commands 3) or 4). TEMPTY - No transmit packets in completion queue. For polling purposes, uses the TX_INT bit in the Interrupt Status Register. TX FIFO PACKET NUMBER - Packet number presently at the output of the TX FIFO. Only valid if TEMPTY is clear. The packet is removed when a TX INT acknowledge is issued.
Note: For software compatibility with future versions, the value read from each FIFO register is intended to be written into the PNR as is, without masking higher bits (provided TEMPTY and REMPTY = 0 respectively).
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BANK 2 OFFSET 6 NAME POINTER REGISTER TYPE READ/WRITE NOT EMPTY is a read only bit
ETEN 0 NOT EMPTY 0 0
SYMBOL PTR
HIGH BYTE
RCV 0
AUTO INCR. 0
READ 0
POINTER HIGH 0 0
LOW BYTE 0 0 0
POINTER LOW 0 0 0 0 0
POINTER REGISTER - The value of this register determines the address to be accessed within the transmit or receive areas. It will auto-increment on accesses to the data register when AUTO INCR. is set. The increment is by one for every byte access, by two for every word access, and by four for every double word access. When RCV is set the address refers to the receive area and uses the output of RX FIFO as the packet number, when RCV is clear the address refers to the transmit area and uses the packet number at the Packet Number Register. READ - Determines the type of access to follow. If the READ bit is high the operation intended is a read. If the READ bit is low the operation is a write. Loading a new pointer value, with the READ bit high, generates a pre-fetch into the Data Register for read purposes. Readback of the pointer will indicate the value of the address last accessed by the CPU (rather than the last pre-fetched). This allows any interrupt routine that uses the pointer, to save it and restore it without affecting the process being interrupted. The Pointer Register should not be loaded until the Data Register FIFO is empty. The NOT EMPTY bit of this register can be read to determine if the FIFO is empty. On reads, if IOCHRDY is not connected to the host, the Data Register (ARDY) should not be read before 370ns after the pointer was loaded to allow the Data Register FIFO to fill. If the pointer is loaded using 8 bit writes, the low byte should be loaded first and the high byte last. ETEN - When set enables EARLY Transmit underrun detection. Normal operation when clear. NOT EMPTY - When set indicates that the Write Data FIFO is not empty yet. The CPU can verify that the FIFO is empty before loading a new pointer value. This is a read only bit.
Note: If AUTO INCR. is not set, the pointer must be loaded with a dword aligned value. BANK 2 OFFSET 8 THROUGH Bh NAME DATA REGISTER
DATA HIGH X X X X DATA LOW X X X X X X X X X X X X
TYPE READ/WRITE
SYMBOL DATA
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DATA REGISTER - Used to read or write the data buffer byte/word presently addressed by the pointer register. This register is mapped into two uni-directional FIFOs that allow moving words to and from the LAN91C110 regardless of whether the pointer address is even, odd or dword aligned. Data goes through the write FIFO into memory, and is prefetched from memory into the read FIFO. If byte accesses are used, the appropriate (next) byte can be accessed through the Data Low or Data High registers. The order to and from the FIFO is preserved. Byte word accesses can be mixed on the fly in any order. This register is mapped into two consecutive word locations. The DATA register is accessible at any address in the 8 through Ah range, while the number of bytes being transferred is determined by A1 and nBE0-nBE. The FIFOs are 12 bytes each.
BANK 2 OFFSET C NAME INTERRUPT STATUS REGISTER
ERCV INT EPH INT RX_OVRN INT 0 ALLOC INT 0
TYPE READ ONLY
TX EMPTY INT 1 TX INT
SYMBOL IST
RCV INT
0
0
0
0
0
OFFSET C
NAME INTERRUPT ACKNOWLEDGE REGISTER
ERCV INT RX_OVRN INT
TYPE WRITE ONLY
SYMBOL ACK
TX EMPTY INT
TX INT
OFFSET D
NAME INTERRUPT MASK REGISTER
ERCV INT MASK EPH INT MASK RX_OVRN INT MASK 0 ALLOC INT MASK 0
TYPE READ/WRITE
TX EMPTY INT MASK 0 0 TX INT MASK
SYMBOL MSK
RCV INT MASK
0
0
0
0
This register can be read and written as a word or as two individual bytes. The Interrupt Mask Register bits enable the appropriate bits when high and disable them when low. A MASK bit being set will cause a hardware interrupt.
Note: The Bit 7 mask must never be written high (1).
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ERCV INT - Early receive interrupt. Set whenever a receive packet is being received, and the number of bytes received into memory exceeds the value programmed as ERCV THRESHOLD (Bank 3, Offset Ch). ERCV INT stays set until acknowledged by writing the INTERRUPT ACKNOWLEDGE REGISTER with the ERCV INT bit set. EPH INT - Set when the Ethernet Protocol Handler section indicates one out of various possible special conditions. This bit merges exception type of interrupt sources, whose service time is not critical to the execution speed of the low level drivers. The exact nature of the interrupt can be obtained from the EPH Status Register (EPHSR), and enabling of these sources can be done via the Control Register. The possible sources are: 1. 2. 3. LINK - Link Test transition CTR_ROL - Statistics counter roll over TXENA cleared - A fatal transmit error occurred forcing TXENA to be cleared. TX_SUC will be low and the specific reason will be reflected by the bits: 3.1) TXUNRN - Transmit under-run 3.2) SQET - SQE Error 3.3) LOST CARR - Lost Carrier 3.4) LATCOL - Late Collision 3.5) 16COL - 16 collisions
Any of the above interrupt sources can be masked by the appropriate ENABLE bits in the Control Register. 1) LE ENABLE (Link Error Enable), 2) CR ENABLE (Counter Roll Over), 3) TE ENABLE (Transmit Error Enable) EPH INT will only be cleared by the following methods: 1. Clearing the LE ENABLE bit in the Control Register if an EPH interrupt is caused by a LINK_OK transition. 2. Reading the Counter Register if an EPH interrupt is caused by statistics counter roll over. 3. Setting TXENA bit high if an EPH interrupt is caused by any of the fatal transmit error listed above (3.1 to 3.5). RX_OVRN INT - Set when 1) the receiver aborts due to an overrun due to a failed memory allocation, 2) the receiver aborts due to a packet length of greater than 2K bytes, or 3) the receiver aborts due to the RCV DISCRD bit in the ERCV register set. The RX_OVRN INT bit latches the condition for the purpose of being polled or generating an interrupt, and will only be cleared by writing the acknowledge register with the RX_OVRN INT bit set. ALLOC INT - Set when an MMU request for TX ram pages is successful. This bit is the complement of the FAILED bit in the ALLOCATION RESULT register. The ALLOC INT bit is cleared by the MMU when the next allocation request is processed or allocation fails. TX EMPTY INT - Set if the TX FIFO goes empty, can be used to generate a single interrupt at the end of a sequence of packets enqueued for transmission. This bit latches the empty condition, and the bit will stay set until it is specifically cleared by writing the acknowledge register with the TX EMPTY INT bit set. If a real time reading of the FIFO empty is desired, the bit should be first cleared and then read. The TX_EMPTY MASK bit should only be set after the following steps: 1. A packet is enqueued for transmission 2. The previous empty condition is cleared (acknowledged) TX INT - Set when at least one packet transmission was completed or any of the below transmit fatal errors occurs: 1. TXUNRN - Transmit under-run 2. SQET - SQE Error 3. LOST CARR - Lost Carrier 4. LATCOL - Late Collision 5. 16COL - 16 collisions The first packet number to be serviced can be read from the FIFO PORTS register. The TX INT bit is always the logic complement of the TEMPTY bit in the FIFO PORTS register. After servicing a packet number, its TX INT interrupt is removed by writing the Interrupt Acknowledge Register with the TX INT bit set. RCV INT - Set when a receive interrupt is generated. The first packet number to be serviced can be read from the FIFO PORTS register. The RCV INT bit is always the logic complement of the REMPTY bit in the FIFO PORTS register. Receive Interrupt is cleared when RX FIFO is empty.
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TX Complete
TXUNRN SQET LOST CARR LATCOL 16COL Fatal Transmit Error DS Q nQ nWRACK NOT EMPTY IntAck1 RCV FIFO
D Q nQ EDGE DETECTOR ON LINK ERR LEMASK IntAck6 CRMASK TEMASK nQ D Q
FIGURE 6 - INTERRUPT STRUCTURE
TXENA
TX_SVC
EPHSR INTERRUPTS MERGED INTO EPH INT
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
S
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ERCV
CTR-ROL
S
SMSC DS - LAN91C110 REV. B
RCV INT TX IntAck2 DS Q nQ FIFO EMPTY TX EMPTY INT TX INT ALLOCATION FAILED RX_OVRN IntAck4 RX_OVRN INT ALLOC INT INT EPH INT ERCV INT 6 5 4 3 2 INTERRUPT STATUS REGISTER nRDIST OE 1 0 6 5 4 3 2 INTERRUPT MASK REGISTER 1 0 nOE MAIN INTERRUPTS D0-7 DATA BUS 16 D8-15
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BANK3 OFFSET 0 THROUGH 7
LOW BYTE 0 HIGH BYTE 0 LOW BYTE 0 HIGH BYTE 0 LOW BYTE 0 HIGH BYTE 0 LOW BYTE 0 HIGH BYTE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
NAME MULTICAST TABLE
TYPE READ/WRITE
MULTICAST TABLE 0 0 0 0 0
SYMBOL MT
0
MULTICAST TABLE 1 0 0 0 0 0
MULTICAST TABLE 2 0 0 0 0 0
MULTICAST TABLE 3 0 0 0 0 0
MULTICAST TABLE 4 0 0 0 0 0
MULTICAST TABLE 5 0 0 0 0 0
MULTICAST TABLE 6 0 0 0 0 0
MULTICAST TABLE 7 0 0 0 0 0
The 64 bit multicast table is used for group address filtering. The hash value is defined as the six most significant bits of the CRC of the destination addresses. The three msb's determine the register to be used (MT0-MT7), while the other three determine the bit within the register. If the appropriate bit in the table is set, the packet is received. If the ALMUL bit in the RCR register is set, all multicast addresses are received regardless of the multicast table values. Hashing is only a partial group addressing filtering scheme, but being the hash value available as part of the receive status word, the receive routine can reduce the search time significantly. With the proper memory structure, the search is limited to comparing only the multicast addresses that have the actual hash value in question.
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BANK 3 OFFSET 8
HIGH BYTE FLTST 0 LOW BYTE 0 0 1 1
NAME MANAGEMENT INTERFACE
MSK_ CRS100 0 1 1
TYPE READ/WRITE
SYMBOL MGMT
0 MDOE 0
0 MCLK 0
1 MDI MDI Pin
1 MDO 0
FLTST - Facilitates the inclusion of packet forwarding information on the receive packet memory structure. When 0, RD0RD7 is always driven. When 1, RD0-RD7 is floated during RECEIVE FRAME STATUS WORD writes (RA2-RA16=0, RCVDMA=1, nRWE0-nRWE3=0). MSK_CRS100 - Disables CRS100 detection during transmit in half duplex mode (SWFDUP=0). MDO - MII Management output. The value of this bit drives the MDO pin. MDI - MII Management input. The value of the MDI pin is readable using this bit. MDCLK - MII Management clock. The value of this bit drives the MDCLK pin. MDOE - MII Management output enable. When high pin MDO is driven, when low pin MDO is tri-stated. The purpose of this interface, along with the corresponding pins is to implement MII PHY management in software.
BANK 3 OFFSET A
HIGH BYTE 0 LOW BYTE 1 0 0 CHIP 0 1 0 0 1 1 0 0 REV 0 0 1 1
NAME REVISION REGISTER
TYPE READ ONLY
SYMBOL REV
CHIP - Chip ID. Can be used by software drivers to identify the device used. REV - Revision ID. Incremented for each revision of a given device.
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CHIP ID VALUE 3 4 5 4* 7 8 9
DEVICE LAN91C90/LAN91C92 LAN91C94 LAN91C95 LAN91C96 LAN91C100 LAN91C100FD LAN91C110
*Note: Shares the chip ID with the LAN91C94. Distinction is made by the revision ID. Revision ID of 6 or higher represents the LAN91C96. OFFSET C
HIGH BYTE 0 LOW BYTE RCV DISCRD 0 0 Reserved 0 0 Reserved 0 1 1 0 0 0 0 0
NAME EARLY RCV REGISTER
TYPE READ/WRITE
SYMBOL ERCV
ERCV THRESHOLD 1 1 1
RCV DISCRD - Set to discard a packet being received. Will discard packets only in the process of being received. When set prior to the end of receive packet, bit 4 (RXOVRN) of the interrupt status register will be set to indicate that the packet was discarded. Otherwise, the packet will be received normally and bit 0 set (RCVINT) in the interrupt status register. RCV DISCRD is self clearing. ERCV THRESHOLD - Threshold for ERCV interrupt. Specified in 64 byte multiples. Whenever the number of bytes written in memory for the presently received packet exceeds the ERCV THRESHOLD, ERCV INT bit of the INTERRUPT STATUS REGISTER is set.
BANK7 OFFSET 0 THROUGH 7 NAME EXTERNAL REGISTERS TYPE SYMBOL
nCSOUT is driven low by the LAN91C110 when a valid access to the EXTERNAL REGISTER range occurs. HIGH BYTE EXTERNAL R/W REGISTER
LOW BYTE
EXTERNAL R/W REGISTER
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CYCLE
AEN=0 A3=0 A4-15 matches I/O BASE BANK SELECT = 7 BANK SELECT = 4,5,6 Otherwise High High
nCSOUT
Driven low. Transparently latched on nADS rising edge.
LAN91C110 DATA BUS
Ignored on writes. Tri-stated on reads.
Ignore cycle. Normal LAN91C110 cycle.
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Typical Flow of Events for Transmit (Auto Release = 0)
S/W DRIVER
1 ISSUE ALLOCATE MEMORY FOR TX - N BYTES - the MMU attempts to allocate N bytes of RAM. WAIT FOR SUCCESSFUL COMPLETION CODE - Poll until the ALLOC INT bit is set or enable its mask bit and wait for the interrupt. The TX packet number is now at the Allocation Result Register. LOAD TRANSMIT DATA - Copy the TX packet number into the Packet Number Register. Write the Pointer Register, then use a block move operation from the upper layer transmit queue into the Data Register. ISSUE "ENQUEUE PACKET NUMBER TO TX FIFO" - This command writes the number present in the Packet Number Register into the TX FIFO. The transmission is now enqueued. No further CPU intervention is needed until a transmit interrupt is generated. The enqueued packet will be transferred to the MAC block as a function of TXENA (nTCR) bit and of the deferral process (1/2 duplex mode only) state. a) Upon transmit completion the first word in memory is written with the status word. The packet number is moved from the TX FIFO into the TX completion FIFO. Interrupt is generated by the TX completion FIFO being not empty. b) If a TX failure occurs on any packets, TX INT is generated and TXENA is cleared, transmission sequence stops. The packet number of the failure packet is presented at the TX FIFO PORTS Register. 7 a) SERVICE INTERRUPT - Read Interrupt Status Register. If it is a transmit interrupt, read the TX FIFO Packet Number from the FIFO Ports Register. Write the packet number into the Packet Number Register. The corresponding status word is now readable from memory. If status word shows successful transmission, issue RELEASE packet number command to free up the memory used by this packet. Remove packet number from completion FIFO by writing TX INT Acknowledge Register. b) Option 1) Release the packet. Option 2) Check the transmit status in the EPH STATUS Register, write the packet number of the current packet to the Packet Number Register, re-enable TXENA, then go to step 4 to start the TX sequence again.
MAC SIDE
2
3
4
5
6
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Typical Flow of Events for Transmit (Auto Release = 1)
S/W DRIVER
1 ISSUE ALLOCATE MEMORY FOR TX - N BYTES - the MMU attempts to allocate N bytes of RAM. WAIT FOR SUCCESSFUL COMPLETION CODE - Poll until the ALLOC INT bit is set or enable its mask bit and wait for the interrupt. The TX packet number is now at the Allocation Result Register. LOAD TRANSMIT DATA - Copy the TX packet number into the Packet Number Register. Write the Pointer Register, then use a block move operation from the upper layer transmit queue into the Data Register. ISSUE "ENQUEUE PACKET NUMBER TO TX FIFO" - This command writes the number present in the Packet Number Register into the TX FIFO. The transmission is now enqueued. No further CPU intervention is needed until a transmit interrupt is generated. The enqueued packet will be transferred to the MAC block as a function of TXENA (nTCR) bit and of the deferral process (1/2 duplex mode only) state. Transmit pages are released by transmit completion. a) The MAC generates a TXEMPTY interrupt upon a completion of a sequence of enqueued packets. b) If a TX failure occurs on any packets, TX INT is generated and TXENA is cleared, transmission sequence stops. The packet number of the failure packet is presented at the TX FIFO PORTS Register. 8 a) SERVICE INTERRUPT - Read Interrupt Status Register, exit the interrupt service routine. b) Option 1) Release the packet. Option 2) Check the transmit status in the EPH STATUS Register, write the packet number of the current packet to the Packet Number Register, re-enable TXENA, then go to step 4 to start the TX sequence again.
MAC SIDE
2
3
4
5
6 7
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Typical Flow of Events for Receive
S/W DRIVER
1 2 ENABLE RECEPTION - By setting the RXEN bit. A packet is received with matching address. Memory is requested from MMU. A packet number is assigned to it. Additional memory is requested if more pages are needed. The internal DMA logic generates sequential addresses and writes the receive words into memory. The MMU does the sequential to physical address translation. If overrun, packet is dropped and memory is released. When the end of packet is detected, the status word is placed at the beginning of the receive packet in memory. Byte count is placed at the second word. If the CRC checks correctly the packet number is written into the RX FIFO. The RX FIFO, being not empty, causes RCV INT (interrupt) to be set. If CRC is incorrect the packet memory is released and no interrupt will occur. SERVICE INTERRUPT - Read the Interrupt Status Register and determine if RCV INT is set. The next receive packet is at receive area. (Its packet number can be read from the FIFO Ports Register). The software driver can process the packet by accessing the RX area, and can move it out to system memory if desired. When processing is complete the CPU issues the REMOVE AND RELEASE FROM TOP OF RX command to have the MMU free up the used memory and packet number.
MAC SIDE
3
4
5
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ISR
Save Bank Select & Address Ptr Registers Mask SMC91C100FD Interrupts
Read Interrupt Register
No Yes Call TX INTR or TXEMPTY INTR
RX INTR?
Yes
TX INTR? No Call RXINTR
Get Next TX
Yes
Packet Available for Transmission?
ALLOC INTR? No No Yes Write Allocated Pkt # into Packet Number Reg. Write Ad Ptr Reg. & Copy Data & Source Address
Call ALLOCATE
Enqueue Packet EPH INTR? Yes Call EPH INTR No Restore Address Pointer & Bank Select Registers Unmask SMC91C100FD Interrupts Set "Ready for Packet" Flag
Return Buffers to Upper Layer
Disable Allocation Interrupt Mask
Exit ISR
FIGURE 7 - INTERRUPT SERVICE ROUTINE
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RX INTR
Write Ad. Ptr. Reg. & Read Word 0 from RAM
Yes
Destination Multicast?
No
Read Words 2, 3, 4 from RAM for Address Filtering
No
Address Filtering Pass?
Yes
No
Status Word OK?
Yes
Do Receive Lookahead
Get Copy Specs from Upper Layer
No
Okay to Copy?
Yes
Copy Data Per Upper Layer Specs
Issue "Remove and Release" Command
Return to ISR
FIGURE 8- RX INTR
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TX INTR
Save Pkt Number Register Read TXDONE Pkt # from FIFO Ports Reg. Write Into Packet Number Register Write Address Pointer Register Read Status Word from RAM
Yes
TX Status OK?
No
Update Statistics
Re-Enable TXENA
Immediately Issue "Release" Command
Update Variables
Acknowledge TXINTR
Read TX INT Again
No
TX INT = 0? Yes Restore Packet Number
Return to ISR
FIGURE 9 - TX INTR
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TXEMPTY INTR
Write Acknowledge Reg. with TXEMPTY Bit Set
Read TXEMPTY & TX INTR
TXEMPTY = 0 & TXINT = 0 (Waiting for Completion)
TXEMPTY = X & TXINT = 1 (Transmission Failed)
TXEMPTY = 1 & TXINT = 0 (Everything went through successfully)
Read Pkt. # Register & Save
Write Address Pointer Register
Read Status Word from RAM
Update Statistics
Issue "Release" Command
Update Variables
Acknowledge TXINTR
Re-Enable TXENA
Restore Packet Number
Return to ISR
FIGURE 10 - TXEMPTY INTR (ASSUMES AUTO RELEASE OPTION SELECTED)
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DRIVER SEND
ALLOCATE
Choose Bank Select Register 2
Issue "Allocate Memory" Command to MMU
Call ALLOCATE
Read Interrupt Status Register
Exit Driver Send
Yes Read Allocation Result Register Write Allocated Packet into Packet # Register Write Address Pointer Register
Allocation Passed?
No
Store Data Buffer Pointer
Clear "Ready for Packet" Flag
Copy Part of TX Data Packet into RAM
Enable Allocation Interrupt
Write Source Address into Proper Location
Copy Remaining TX Data Packet into RAM
Enqueue Packet
Set "Ready for Packet" Flag
Return Buffers to Upper Layer
Return
FIGURE 11 - DRIVE SEND AND ALLOCATE ROUTINES
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MEMORY PARTITIONING
Unlike other controllers, the LAN91C110 does not require a fixed memory partitioning between transmit and receive resources. The MMU allocates and de-allocates memory upon different events. An additional mechanism allows the CPU to prevent the receive process from starving the transmit memory allocation. Memory is always requested by the side that needs to write into it, that is: the CPU for transmit or the MAC for receive. The CPU can control the number of bytes it requests for transmit but it cannot determine the number of bytes the receive process is going to demand. Furthermore, the receive process requests will be dependent on network traffic, in particular on the arrival of broadcast and multicast packets that might not be for the node, and that are not subject to upper layer software flow control. In order to prevent unwanted traffic from using too much memory, the CPU can program a "memory reserved for transmit" parameter. If the free memory falls below the "memory reserved for transmit" value, MMU requests from the MAC block will fail and the packets will overrun and be ignored. Whenever enough memory is released, packets can be received again. If the reserved value is too large, the node might lose data which is an abnormal condition. If the value is kept at zero, memory allocation is handled on first-come first-served basis for the entire memory capacity. Note that with the memory management built into the LAN91C110, the CPU can dynamically program this parameter. For instance, when the driver does not need to enqueue transmissions, it can allow more memory to be allocated for receive (by reducing the value of the reserved memory). Whenever the driver needs to burst transmissions it can reduce the receive memory allocation. The driver program the parameter as a function of the following variables: 1. 2. Free memory (read only register) Memory size (read only register)
The reserved memory value can be changed on the fly. If the MEMORY RESERVED FOR TX value is increased above the FREE MEMORY, receive packets in progress are still received, but no new packets are accepted until the FREE MEMORY increases above the MEMORY RESERVED value.
INTERRUPT GENERATION
The interrupt strategy for the transmit and receive processes is such that it does not represent the bottleneck in the transmit and receive queue management between the software driver and the controller. For that purpose there is no register reading necessary before the next element in the queue (namely transmit or receive packet) can be handled by the controller. The transmit and receive results are placed in memory. The receive interrupt will be generated when the receive queue (FIFO of packets) is not empty and receive interrupts are enabled. This allows the interrupt service routine to process many receive packets without exiting, or one at a time if the ISR just returns after processing and removing one. There are two types of transmit interrupt strategies: 1. 2. One interrupt per packet. One interrupt per sequence of packets.
The strategy is determined by how the transmit interrupt bits and the AUTO RELEASE bit are used. TX INT bit - Set whenever the TX completion FIFO is not empty. TX EMPTY INT bit - Set whenever the TX FIFO is empty. AUTO RELEASE - When set, successful transmit packets are not written into completion FIFO, and their memory is released automatically. 1. One interrupt per packet: enable TX INT, set AUTO RELEASE=0. The software driver can find the completion result in memory and process the interrupt one packet at a time. Depending on the completion code the driver will take different actions. Note that the transmit process is working in parallel and other transmissions might be taking place. The LAN91C110 is virtually queuing the packet numbers and their status words.
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In this case, the transmit interrupt service routine can find the next packet number to be serviced by reading the TX FIFO PACKET NUMBER at the FIFO PORTS register. This eliminates the need for the driver to keep a list of packet numbers being transmitted. The numbers are queued by the LAN91C110 and provided back to the CPU as their transmission completes. 2. One interrupt per sequence of packets: Enable TX EMPTY INT and TX INT, set AUTO RELEASE=1. TX EMPTY INT is generated only after transmitting the last packet in the FIFO. TX INT will be set on a fatal transmit error allowing the CPU to know that the transmit process has stopped and therefore the FIFO will not be emptied. This mode has the advantage of a smaller CPU overhead, and faster memory de-allocation. Note that when AUTO RELEASE=1 the CPU is not provided with the packet numbers that completed successfully.
Note: The pointer register is shared by any process accessing the LAN91C110 memory. In order to allow processes to be interruptable, the interrupting process is responsible for reading the pointer value before modifying it, saving it, and restoring it before returning from the interrupt.
Typically there would be three processes using the pointer: 1. 2. 3. Transmit loading (sometimes interrupt driven) Receive unloading (interrupt driven) Transmit Status reading (interrupt driven).
1) and 3) also share the usage of the Packet Number Register. Therefore saving and restoring the PNR is also required from interrupt service routines.
INTERRUPT STATUS REGISTER RCV INT PACKET NUMBER REGISTER
'NOT EMPTY' RX FIFO PACKET NUMBER
TWO OPTIONS
TX EMPTY INT TX INT ALLOC INT
TX FIFO RX FIFO
'EMPTY' RX PACKET NUMBER
TX COMPLETION FIFO 'NOT EMPTY'
TX DONE PACKET NUMBER CPU ADDRESS CSMA ADDRESS
CSMA/CD
LOGICAL ADDRESS
PACKET #
MMU
M.S. BIT ONLY PACK # OUT
PHYSICAL ADDRESS
RAM
FIGURE 12 - INTERRUPT GENERATION FOR TRANSMIT, RECEIVE, MMU
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OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS*
Operating Temperature Range ................................................................................................................ 0 EC to +70EC Storage Temperature Range .............................................................................................................-55ECto + 150EC Lead Temperature Range ......................................................................................... Refer to JEDEC Spec. J-STD-020 Positive Voltage on any pin, with respect to Ground ......................................................................................VCC + 0.3V Negative Voltage on any pin, with respect to Ground ............................................................................................ -0.3V Maximum VCC ........................................................................................................................................................... +7V *Stresses above those listed above could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied.
Note: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used.
DC ELECTRICAL CHARACTERISTICS
(TA = 0EC - 70EC, VCC = +5.0 V 10%)
PARAMETER I Type Input Buffer
Low Input Level High Input Level
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
VILI VIHI 2.0
0.8
V V
TTL Levels
IS Type Input Buffer
Low Input Level High Input Level Schmitt Trigger Hysteresis VILIS VIHIS VHYS 2.2 250 0.8 V V mV Schmitt Trigger Schmitt Trigger
ICLK Input Buffer
Low Input Level High Input Level VILCK VIHCK 3.0 0.4 V V
Input Leakage (All I and IS buffers except pins with pullups/pulldowns)
Low Input Leakage High Input Leakage IIL IIH -10 -10 +10 +10 A A VIN = 0 VIN = VCC
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PARAMETER O4 Type Buffer
Low Output Level High Output Level Output Leakage
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
VOL VOH IOL 2.4 -10
0.4
V V
IOL = 4 mA IOH = -2 mA VIN = 0 to VCC
+10
A
I/O4 Type Buffer
Low Output Level High Output Level Output Leakage VOL VOH IOL 2.4 -10 +10 0.4 V V A IOL = 4 mA IOH = -2 mA VIN = 0 to VCC
I/O8 Type Buffer
Low Output Voltage High Output Voltage Output Leakage VOL VOH IOL 2.4 -10 +10 0.4 V V A IOL = 8 mA IOH = -4 mA VIN = 0 to VCC
O12 Type Buffer
Low Output Level High Output Level Output Leakage VOL VOH IOL 2.4 -10 +10 0.5 V V A IOL = 12 mA IOH = -6 mA VIN = 0 to VCC
OD16 Type Buffer
Low Output Level Output Leakage Supply Current Active Supply Current Standby VOL IOL ICC ICSBY -10 60 8 0.5 +10 95 V A mA mA IOL = 16 mA VIN = 0 to VCC All outputs open.
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CAPACITANCE TA = 25EC; fc = 1MHz; VCC = 5V PARAMETER Clock Input Capacitance
Input Capacitance Output Capacitance
SYMBOL CIN
CIN COUT
MIN
LIMITS TYP
MAX 20
10 20
UNIT pF
pF pF
TEST CONDITION All pins except pin under test tied to AC ground
CAPACITIVE LOAD ON OUTPUTS
ARDY, D0-D15 All other outputs 240 pF 45 pF
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TIMING DIAGRAMS
ADDRESS nADS t3 READ DATA nRD, nWR t1 t2 t4 A1-A15, AEN, nBE0-nBE1 valid
t5 WRITE DATA D0-D15 valid
t5A
FIGURE 13 - ASYNCHRONOUS CYCLE - NADS=0
t1 t2 t3 t4 t5 t5A
PARAMETER A1-A15, AEN, nBE0-nBE1 Valid and nADS Low Setup to nRD, nWR Active A1-A15, AEN, nBE0-nBE1 Hold After nRD, nWR Inactive (Assuming nADS Tied Low) nRD Low to Valid Data nRD High to Data Floating Data Setup to nWR Inactive Data Hold After nWR Inactive
MIN 25
20
TYP
MAX
UNITS ns
ns
40 30 30 5
ns ns ns ns
ADDRESS
A1-A15, AEN, nBE0-nBE1 valid t8 t9
nADS t3 READ DATA nRD, nWR t1 t4
t5 WRITE DATA D0-D15 valid
t5A
FIGURE 14 - ASYNCHRONOUS CYCLE - USING NADS
t1 t3 t4 t5 t5A t8 t9
PARAMETER A1-A15, AEN, nBE0-nBE1 Valid and nADS Low Setup to nRD, nWR Active nRD Low to Valid Data nRD High to Data Floating Data Setup to nWR Inactive Data Hold After nWR Inactive A1-A15, AEN, nBE0-nBE1 Setup to nADS Rising A1-A15, AEN, nBE0-nBE1 Hold after nADS Rising
MIN 25
TYP
MAX
UNITS ns
ns ns ns ns ns ns
40 30 30 5 10 15
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nADS
t8 ADDRESS A1-A15, AEN, nBE0-nBE1 t25 nLDEV
t9
FIGURE 15 - ADDRESS LATCHING FOR ALL MODES
t8 t9 t25
PARAMETER A1-A15, AEN, nBE0-nBE1 Setup to nADS Rising A1-A15, AEN, nBE0-nBE1 Hold After nADS Rising A4-A15, AEN to nLDEV Delay
MIN 10 15
TYP
MAX
20
UNITS ns ns ns
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t50 t54 t34 RA2-RA16 t39 t36 nRWE0-nRWE3 t52 nROE RD0-RD31 t37 t35 t38
t50 t51
t53
WRITE CYCLE
t50 t54 t51 t34
READ CYCLE
t50 t38 RA2-RA16
t35
t39 t36 nRWE0-nRWE3 t52 nROE RD0-RD31 t53 t37
READ CYCLE
t50 t38 RA2-RA16 nRWE0-nRWE3 t52 nROE RD0-RD31 t51 t38
WRITE CYCLE
t51 t38
t51 t38
MULTIPLE READ CYCLES
FIGURE 16 - SRAM INTERFACE
PARAMETER Write - RA2-RA16 Setup to nRWE0-nRWE3 Falling Write - RA2-RA16 Hold after nRWE0-nRWE3 Rising Write - RD0-RD31 Setup to nRWE0-nRWE3 Rising Write - RD0-RD31 Hold after nRWE0-nRWE3 Rising Write - nRWE0-nRWE3 Pulse Width Write - RA2-RA16 Valid to End of Write Read - RA2-RA16 Valid to RD0-RD31 Valid Read - RD0-RD31 Hold after RA2-RA16 Change Read - nROE enable to RD0-RD31 Valid Read - nROE disable to RD0-RD31 Invalid Read/Write - Cycle Time MIN 0 0 12 0 15 12 3 0 25 12 8 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns
t34 t35 t36 t37 t39 t54 t38 t51 t52 t53 t50
15
SMSC DS - LAN91C110 REV. B
Page 51
Rev. 09/05/02
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
APPLICATION NOTE The following is the list of potential SRAMs and suppliers for the LAN91C110 Rev B. These SRAMs meet all timing requirements for LAN91C110 Rev B. But any other SRAM that meets the specification will also work with the LAN91C110 Rev B.
Min 3ns Max15ns Min25ns Max12ns Max8ns Min12ns Min12ns Min15ns Manufacturer Part # t51 Data t38 Hold after Address Address Valid to Change Data Valid 3 10 3 3 3 3 3 3 3 3 3 3 3 3 4 4 3 3 3 3 3 12 15 12 15 10 12 10 12 15 10 12 15 12 15 12 15 10 12 15 R/W Cycle 10 12 15 12 15 10 12 10 12 15 10 12 15 12 15 12 15 10 12 15 Output nROE Enable to Disable to Output Output in Valid High Z 5 5 5 7 5 6 5 6 5 5 7 5 6 7 7 8 6 7 5 6 7 6 7 3 4 5 6 5 5 7 5 6 7 6 6 6 6 5 6 7 Address Valid to End of Write 9 10 11 8 10 9 10 7 9 10 7 8 10 9 10 9 10 8 9 10 Data Setup to End of Write 5 6 7 6 8 6 7 5 8 9 5 6 8 7 8 6 7 5 6 7 Write Pulse Width 7 8 10 8 9 9 10 7 8 9 7 8 10 9 10 8 10 8 9 10
ISSI ISSI ISSI Alliance Alliance Winbond Winbond Cypress Cypress Cypress Cypress Cypress Cypress IDT IDT IDT IDT SamSung SamSung SamSung
IS61C3216-10 IS61C3216-12 IS61C3216-15 AS7C256-12 AS7C256-15 24257AJ-10 24257AJ-12 CY7C199-10VC CY7C199-12VC CY7C199-15VC CY7C1021-10 CY7C1021-12 CY7C1021-15 IDT71016S12 IDT71016S15 IDT71256SA12 IDT71256SA15 K6E0808C1E-C10 K6E0808C1E-C12 K6E0808C1E-C15
SMSC DS - LAN91C110 REV. B
Page 52
Rev. 09/05/02
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
TX25 TXD0-TXD3 t27 TXEN100 t28 RXD0-RXD3 t28 RX25 t29 RX_DV t29 RX_ER t28 t27
FIGURE 17 - MII INTERFACE
t27 t28 t29
PARAMETER TXD0-TXD3, TXEN100 Delay from TX25 Rising RXD0-RXD3, RX_DV, RX_ER Setup to RX25 Rising RXD0-RXD3, RX_DV, RX_ER Hold After RX25 Rising
MIN 0 10 10
TYP
MAX 15
UNITS ns ns ns
SMSC DS - LAN91C110 REV. B
Page 53
Rev. 09/05/02
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
FIGURE 18 - 144 PIN TQFP PACKAGE OUTLINES
TABLE 4 - PIN PACKAGE OUTLINE TABLE
A A1 A2 D D/2 D1 E E/2 E1 H L L1 e W R1 R2 ccc ccc
MIN ~ 0.05 0.95 21.80 10.90 19.80 21.80 10.90 19.80 0.09 0.45 ~
0o 0.13 0.08 0.08 ~ ~
NOMINAL 1.0 0.10 1.00 22.00 11.00 20.00 22.00 11.00 20.00 ~ 0.60 1.00 0.50 Basic 3.5o 0.18 ~ ~ ~ ~
MAX 1.20 0.15 1.05 22.20 11.10 20.20 22.20 11.10 20.20 0.20 0.75 ~
7o 0.23 ~ 0.20 0.0762 0.08
REMARK Overall Package Height Standoff Body Thickness X Span 1 /2 X Span Measure from Centerline X body Size Y Span 1 /2 Y Span Measure from Centerline Y body Size Lead Frame Thickness Lead Foot Length from Centerline Lead Length Lead Pitch Lead Foot Angle Lead Width Lead Shoulder Radius Lead Foot Radius Max Coplanarity (Assemblers) Max Coplanarity (Test House)
Note 1: Controlling Unit: millimeter Note 2: Tolerance on the position of the leads is 0.04 mm maximum. Note 3: Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion Is 0.25 mm. Note 4: Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane is 0.781.08 mm. Note 5: Details of pin 1 identifier are optional but must be located within the zone indicated.
SMSC DS - LAN91C110 REV. B
Page 54
Rev. 09/05/02

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